(no subject)
with apologies to those who don't speak HDL/Verilog - this post is mainly to laugh at my own stupidity, and convincce m e that multiple 14-hour code sessions may not be a good idea. As the penguins said, "Just smile and nod, guys".
I just spent five hours chasing a bug I introduced while 'cleaning up' some code. Check it out.
Before, working code:
wire combreset;
assign combreset = ( !rst_n || !cryptgoing);
always @(posedge clk or negedge rst_n) begin
if ( !rst_n ) begin
.. reset logic ..
end else begin
if (!cryptgoing) begin
.. reset logic ..
end else begin
.. crypt logic ..
end
end
end
Optimised (and totally fucking different, broken beyond all recognition):
wire combreset;
assign combreset = ( !rst_n || !cryptgoing);
always @(posedge clk or posedge combreset) begin
if ( combreset ) begin
.. reset logic ..
end else begin
.. crypt logic ..
end
end
They aren't exact code snippets, so there may be typos in there. SERIOUSLY THOUGH, WHAT THE FUCK?!
For a start, cryptgoing becomes aynchronous to clk in the broken version. This doesn't show up in a fucking simulation, though, and it all passes (since my generated signals are all sync to clock anyway, and glitchfreeish). How the fuck I didn't see that while writing/debugging, I have no clue. Additionally, there's no bastarding check on cryptgoing any more - ie, the crypt logic is executed irrelevant of the start of cryptgoing (which is very bad).
I just spent five hours chasing a bug I introduced while 'cleaning up' some code. Check it out.
Before, working code:
wire combreset;
assign combreset = ( !rst_n || !cryptgoing);
always @(posedge clk or negedge rst_n) begin
if ( !rst_n ) begin
.. reset logic ..
end else begin
if (!cryptgoing) begin
.. reset logic ..
end else begin
.. crypt logic ..
end
end
end
Optimised (and totally fucking different, broken beyond all recognition):
wire combreset;
assign combreset = ( !rst_n || !cryptgoing);
always @(posedge clk or posedge combreset) begin
if ( combreset ) begin
.. reset logic ..
end else begin
.. crypt logic ..
end
end
They aren't exact code snippets, so there may be typos in there. SERIOUSLY THOUGH, WHAT THE FUCK?!
For a start, cryptgoing becomes aynchronous to clk in the broken version. This doesn't show up in a fucking simulation, though, and it all passes (since my generated signals are all sync to clock anyway, and glitchfreeish). How the fuck I didn't see that while writing/debugging, I have no clue. Additionally, there's no bastarding check on cryptgoing any more - ie, the crypt logic is executed irrelevant of the start of cryptgoing (which is very bad).