So, today I'm going to stop work on the bitcoin mining FPGA implementation ( Read more... )

After hunting through Xilinx docs for many hours, I find this.


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Apologies if this post is crazy/doesn't make sense. I haven't slept for a long, long time, and when I did sleep, I saw code. Really. I saw waveforms of digital logic simulations, I saw new techniques, I anticipated new problems.So, LJ, great things today. Really great things ( Read more... )

AAAAAAAND IT WORKS!

Protip:


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with apologies to those who don't speak HDL/Verilog - this post is mainly to laugh at my own stupidity, and convincce m e that multiple 14-hour code sessions may not be a good idea. As the penguins said, "Just smile and nod, guys".I just spent five hours chasing a bug I introduced while 'cleaning up' some code. Check it out ( Read more... )

Got back in Bradford about 11PM-ish ( Read more... )