Ну, почти.
runningSumMaybes.vhdl:75:36: port "generated_temporary_name_1" cannot be readЕсть у VHDL особенность поведения: сигнал типа out нельзя читать в сущности, что этом сигналом управляет.
Вот это - последняя ошибка. Надеюсь.
-------------------------------------------------------------------------------
-- Entity declaration and architecture for runningSumMaybes_1.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
entity runningSumMaybes_1 is
port (
generated_temporary_name_0 : in unsigned (8 downto 0);
generated_temporary_name_1 : out unsigned (7 downto 0);
Hardware_HHDL_Examples_Clock_Clk: in std_logic;
Hardware_HHDL_Examples_Clock_Reset: in std_logic
);
end entity runningSumMaybes_1;
architecture hhdl_generated of runningSumMaybes_1 is
pure function select_func(s : in bit; t, f : in bit) return bit is
begin
if s = '1' then
return t;
else
return f;
end if;
end function select_func;
pure function select_func(s : in bit; t, f : in unsigned) return unsigned is
begin
if s = '1' then
return t;
else
return f;
end if;
end function select_func;
pure function bit_equality(a, b : in bit) return bit is
begin
if a = b then
return '1';
else
return '0';
end if;
end function bit_equality;
pure function bit_equality(a, b : in unsigned) return bit is
begin
if a = b then
return '1';
else
return '0';
end if;
end function bit_equality;
signal generated_temporary_name_19 : unsigned (7 downto 0);
signal generated_temporary_name_18 : unsigned (7 downto 0);
signal generated_temporary_name_17 : unsigned (7 downto 0);
signal generated_temporary_name_16 : unsigned (7 downto 0);
signal generated_temporary_name_15 : unsigned (7 downto 0);
signal generated_temporary_name_14 : unsigned (7 downto 0);
signal generated_temporary_name_13 : unsigned (8 downto 0);
signal generated_temporary_name_12 : bit;
signal generated_temporary_name_11 : bit;
signal generated_temporary_name_10 : bit;
signal generated_temporary_name_9 : bit;
signal generated_temporary_name_8 : unsigned (8 downto 0);
signal generated_temporary_name_7 : bit;
signal generated_temporary_name_6 : bit;
signal generated_temporary_name_5 : bit;
signal generated_temporary_name_4 : bit;
signal generated_temporary_name_3 : bit;
signal generated_temporary_name_2 : unsigned (8 downto 0);
begin
generated_temporary_name_19 <= generated_temporary_name_1 + generated_temporary_name_18;
process (Hardware_HHDL_Examples_Clock_Clk, Hardware_HHDL_Examples_Clock_Reset) is
begin
if Hardware_HHDL_Examples_Clock_Reset = '0' then
generated_temporary_name_1 <= "00000000";
elsif rising_edge(Hardware_HHDL_Examples_Clock_Clk) then
generated_temporary_name_1 <= generated_temporary_name_19;
end if;
end process;
generated_temporary_name_18 <= select_func(generated_temporary_name_7, generated_temporary_name_16, generated_temporary_name_17);
generated_temporary_name_17 <= "00000000";
generated_temporary_name_16 <= generated_temporary_name_15;
generated_temporary_name_15 <= generated_temporary_name_14;
generated_temporary_name_14 <= generated_temporary_name_13 ( 7 downto 0 );
generated_temporary_name_13 <= generated_temporary_name_0;
generated_temporary_name_12 <= generated_temporary_name_7 and generated_temporary_name_11;
generated_temporary_name_11 <= bit_equality( generated_temporary_name_9, generated_temporary_name_10);
generated_temporary_name_10 <= '0';
generated_temporary_name_9 <= generated_temporary_name_8 ( 8 );
generated_temporary_name_8 <= generated_temporary_name_0;
generated_temporary_name_7 <= generated_temporary_name_6 and generated_temporary_name_5;
generated_temporary_name_6 <= '1';
generated_temporary_name_5 <= bit_equality( generated_temporary_name_3, generated_temporary_name_4);
generated_temporary_name_4 <= '1';
generated_temporary_name_3 <= generated_temporary_name_2 ( 8 );
generated_temporary_name_2 <= generated_temporary_name_0;
end architecture hhdl_generated;
Такая портянка получается из вот этого красивого и аккуратного кода:
-- Many extensions. I overload many things from Haskell Prelude in the style
-- of Awesome Prelude. Also you may need a Template Haskell transformations
-- on declarations, which derives classes and type families instances, etc, etc.
{-# LANGUAGE TypeFamilies, TypeOperators, FlexibleContexts, DoRec #-}
{-# LANGUAGE DeriveDataTypeable, NoImplicitPrelude, TemplateHaskell #-}
{-# LANGUAGE UndecidableInstances #-}
module Hardware.HHDL.Examples.RunningSumMaybes where
import Data.Word
-- The main module of the library. It exports everything I deemed useful
-- for hardware description - code generation over ADT, netlist operators, some
-- handy functions from Prelude...
-- Also, it contains making of wires for Either and Maybe and matching functions.
import Hardware.HHDL
-- The description of clocking frequency for our example.
import Hardware.HHDL.Examples.Clock
-------------------------------------------------------------------------------
-- How to pattern match an algebraic type.
-- Clocked is a type of entity. It has three arguments: a list of clocking frequencies allowed
-- in netlist, types of inputs and outputs.
runningSumMaybes :: Clock c => Mealy c (Wire c (Maybe Word8) :. Nil) (Wire c Word8 :. Nil)
runningSumMaybes = mkMealy (0 :. Nil) "runningSumMaybes" $ \(sum :. Nil) (mbA :. Nil) -> do
-- here we pattern match in the "First class patterns" style.
-- the idea is that for each constructor Cons of algebraic type T we automatically
-- create two functions:
-- - mkCons which creates a wire (of type Wire c T) from wires of arguments and
-- - pCons which matches a wire of type Wire c T with patterns of types of Cons
-- arguments.
-- pJust and pNothing were generated in Hardware.HHDL.HHDL from the description of
-- Maybe type.
-- pvar is a pattern that matches anything and passes that anything as an argument
-- to processing function.
a <- match mbA [
-- if we have Just x, return x!
pJust pvar --> \(x :. Nil) -> return x
-- default with 0, if Nothing.
, pNothing --> \Nil -> return (constant 0)
]
-- compute the sum.
nextSum <- assignWire (sum + a)
-- return currently locked sum.
return (nextSum :. Nil, sum :. Nil)
-- How to obtain VHDL text - we fix polymorphic parameters in Clocked, generate text (with any
-- entities we have to use) and pass it to display and write function.
runningSumMaybesVHDLText = writeHDLText VHDL (runningSumMaybes :: Mealy Clk (Wire Clk (Maybe Word8) :. Nil) (Wire Clk Word8 :. Nil))
(\s -> putStrLn s >> writeFile "runningSumMaybes.vhdl" s)
-- a shortcut.
test = runningSumMaybesVHDLText
Жирным выделил строки кода.
Используется машина Мили, поэтому защёлкивание неявное. На вход функции поступают текущее состояние и входы, на выходе она должна дать следующее состояние и выходы.
Надо ещё придумать, как давать разумные имена входам и выходам. Но всё равно надеюсь закончить к концу выходных.