SemiWiki - Graphical DRC vs Text-based DRC
http://www.semiwiki.com/forum/content/519-graphical-drc-vs-text-based-drc.html
IC designs go through a layout process and then a verification of that layout to determine if the layout layer width and spacing rules conform to a set of manufacturing design rules. Adhering to the layout rules will ensure that your chip has acceptable yields.
At the 28nm node a typical DRC (Design Rule Check) deck will have about 2,500 rules which requires that a fab engineer writes about 15,000 lines to check those rules...
IC designs go through a layout process and then a verification of that layout to determine if the layout layer width and spacing rules conform to a set of manufacturing design rules. Adhering to the layout rules will ensure that your chip has acceptable yields.
At the 28nm node a typical DRC (Design Rule Check) deck will have about 2,500 rules which requires that a fab engineer writes about 15,000 lines to check those rules...