Что нашел в кодогенераторе GCC.
ev6.md:
; EV6 can issue 4 insns per clock. It's out-of-order, so this isn't
; expected to help over-much, but a precise description can be important
; for software pipelining.
;
; EV6 has two symmetric pairs ("clusters") of two asymmetric integer
; units ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
;
; ??? The clusters have independent register files that are re-synced
; every cycle. Thus there is one additional cycle of latency between
; insns issued on different clusters. Possibly model that by duplicating
; all EBOX insn_reservations that can issue to either cluster, increasing
; all latencies by one, and adding bypasses within the cluster.
;
; ??? In addition, instruction order affects cluster issue.
...
; Conditional moves decompose into two independent primitives, each taking
; one cycle. Since ev6 is out-of-order, we can't see anything but two cycles.
Последнее означает, что они внутри еще и разбивали сложные команды на более простые!
(в нашей модели MIPS команда условного перехода создавала две команды: вычисления условия и вычисления адреса. Мы, значить, не глупее DEC оказались. Отлично.;)
ev5.md:
; Multiplies use a non-pipelined imul unit. Also, "no insn can be issued
; to E0 exactly two cycles before an integer multiply completes".
Но это еще не все.
; The floating point divider is not pipelined. Also, "no FPOP insn can be
; issued exactly five or exactly six cycles before an fdiv insn completes".
Какая, однако, это странная архитектура, DEC Alpha. ;)
; EV6 can issue 4 insns per clock. It's out-of-order, so this isn't
; expected to help over-much, but a precise description can be important
; for software pipelining.
;
; EV6 has two symmetric pairs ("clusters") of two asymmetric integer
; units ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
;
; ??? The clusters have independent register files that are re-synced
; every cycle. Thus there is one additional cycle of latency between
; insns issued on different clusters. Possibly model that by duplicating
; all EBOX insn_reservations that can issue to either cluster, increasing
; all latencies by one, and adding bypasses within the cluster.
;
; ??? In addition, instruction order affects cluster issue.
...
; Conditional moves decompose into two independent primitives, each taking
; one cycle. Since ev6 is out-of-order, we can't see anything but two cycles.
Последнее означает, что они внутри еще и разбивали сложные команды на более простые!
(в нашей модели MIPS команда условного перехода создавала две команды: вычисления условия и вычисления адреса. Мы, значить, не глупее DEC оказались. Отлично.;)
ev5.md:
; Multiplies use a non-pipelined imul unit. Also, "no insn can be issued
; to E0 exactly two cycles before an integer multiply completes".
Но это еще не все.
; The floating point divider is not pipelined. Also, "no FPOP insn can be
; issued exactly five or exactly six cycles before an fdiv insn completes".
Какая, однако, это странная архитектура, DEC Alpha. ;)