Еще про нетактируемые (clockless) процессоры.
Вот еще одно (старое) обсуждение нетактируемых процессоров на слешдоте.
Там, среди всего прочего, есть и такая цитата:
Way Back When (Score:5, Interesting)
by opos (681974) on Tuesday November 02, @07:22AM (#10698567)
(http://frank.itlab.us/)
A long long time ago (1970s) Charlie Molnar, designer of the Linc tape (the Linc computer was an NIH funded (late 1960s) minicomputer that evolved into the PDP 8 and pushed DEC into the minicompuer business) explored asynchronous computing. Along the way they discovered synchronizer failure - i.e. the inability to reliably synchronize asyncronous subsystems - see Chaney, T.J. and Molnar, C.E. 1973. Anomalous behavior of synchronizer and arbiter circuits. IEEE Trans. Comp. pages 421-422. The bottom line is that it is physically impossible to guarantee that the data setup requirements (the minimum time the data must be asserted before it can be reliably clocked into the flip flop) of a flip flop can be met when the clock is asserted by one async component and the data are asserted by another async component. To my knowledge, this fundamental limitation has never been overcome.
А вот диссертация с опровержением этого тезиса: http://www-sccm.stanford.edu/~mitchell/masters.html с интересным названием "Proving Newtonian Arbiters Correct, Almost Surely." ;)
Пока времени смотреть нет, это для интересующихся и себе в закладки.
Там, среди всего прочего, есть и такая цитата:
Way Back When (Score:5, Interesting)
by opos (681974) on Tuesday November 02, @07:22AM (#10698567)
(http://frank.itlab.us/)
A long long time ago (1970s) Charlie Molnar, designer of the Linc tape (the Linc computer was an NIH funded (late 1960s) minicomputer that evolved into the PDP 8 and pushed DEC into the minicompuer business) explored asynchronous computing. Along the way they discovered synchronizer failure - i.e. the inability to reliably synchronize asyncronous subsystems - see Chaney, T.J. and Molnar, C.E. 1973. Anomalous behavior of synchronizer and arbiter circuits. IEEE Trans. Comp. pages 421-422. The bottom line is that it is physically impossible to guarantee that the data setup requirements (the minimum time the data must be asserted before it can be reliably clocked into the flip flop) of a flip flop can be met when the clock is asserted by one async component and the data are asserted by another async component. To my knowledge, this fundamental limitation has never been overcome.
А вот диссертация с опровержением этого тезиса: http://www-sccm.stanford.edu/~mitchell/masters.html с интересным названием "Proving Newtonian Arbiters Correct, Almost Surely." ;)
Пока времени смотреть нет, это для интересующихся и себе в закладки.