STM32 F7
Компания STMicroelectronics объявила о скором выпуске микроконтроллеров с ядром Cortex М7. Опытные образцы будут доступны ориентировочно в 1-ом квартале 2015 г. Отличительной особенностью новой серии является увеличение производительности в 2 раза (428 DMIPS) в сравнении с Cortex M4 (210 DMIPS) при частоте ядра 200 Мгц.
Smart architecture with new peripheral set:
The STM32 F7 series unleashes the new Cortex M7 core:
-AXI and multi-AHB bus matrix for interconnecting Core, peripherals and memories
-Two general purpose DMA controllers and dedicated DMAs for Ethernet, high-speed USB On-The-Go and the Chrom-ART graphic accelerator.
-Peripheral speed independent from CPU speed (dual clock support) allowing system clock changes without impacting the function of the peripherals
-Even more peripherals, such as two serial audio interfaces (SAI) with SPDIF output support, three I2S half-duplex with SPDIF input support, two USB OTG with dedicated power supply and Dual Quad SPI interface
-320KBytes of SRAM with scattered architecture:
---240 Kbytes of universal data memory
---a 16 Kbytes partition for sharing data over the bus matrix
---64 Kbytes of Tightly-Coupled Data Memory (DTCM) for time critical data handling (stack, heap...)
---16 Kbytes of Tightly-Coupled Instruction Memory (ITCM) for time critical routines
---4 Kbytes of backup SRAM to keep data in the lowest power modes.
Power efficiency:
-7 CoreMark/mW at 1.8V and 180 MHz
-120µA typical current consumption in Stop mode with all context and SRAM saved
Compatibility:
-Cortex M7 is backward compatible with Cortex M4 instruction set
-STM32 F7 series is pin-to-pin compatible to the STM32 F4 series
За наводку спасибо 32bit_me
Smart architecture with new peripheral set:
The STM32 F7 series unleashes the new Cortex M7 core:
-AXI and multi-AHB bus matrix for interconnecting Core, peripherals and memories
-Two general purpose DMA controllers and dedicated DMAs for Ethernet, high-speed USB On-The-Go and the Chrom-ART graphic accelerator.
-Peripheral speed independent from CPU speed (dual clock support) allowing system clock changes without impacting the function of the peripherals
-Even more peripherals, such as two serial audio interfaces (SAI) with SPDIF output support, three I2S half-duplex with SPDIF input support, two USB OTG with dedicated power supply and Dual Quad SPI interface
-320KBytes of SRAM with scattered architecture:
---240 Kbytes of universal data memory
---a 16 Kbytes partition for sharing data over the bus matrix
---64 Kbytes of Tightly-Coupled Data Memory (DTCM) for time critical data handling (stack, heap...)
---16 Kbytes of Tightly-Coupled Instruction Memory (ITCM) for time critical routines
---4 Kbytes of backup SRAM to keep data in the lowest power modes.
Power efficiency:
-7 CoreMark/mW at 1.8V and 180 MHz
-120µA typical current consumption in Stop mode with all context and SRAM saved
Compatibility:
-Cortex M7 is backward compatible with Cortex M4 instruction set
-STM32 F7 series is pin-to-pin compatible to the STM32 F4 series
За наводку спасибо 32bit_me