4 HiTech Jobs (LSI design and verification) in Ramat-Gan, Cavium
ASIC Design Engineer
Job Grade Principal
Hiring Location(s) Ramat Gan, Israel
Regular Full-time
Requisition type: Replacement / Addition / Immigration / Extension / Conversion Addition
Planned start date, and if appropriate, planned term date (term date for Interns, Temps, or Contractors) 10/1/2016
Budgeted salary range (local currency): Salary average for his grade for this level: XXX NIS. Salary will be match according to the candidate’s experience.
Role & responsibilities
• Key Responsibilities
• Additional individual Contributor / Technical responsibilities AND/OR People Management responsibilities
Member of the design team that is responsible for developing complex, state of the art high-speed Ethernet controller chips.
The candidate will own tasks such as micro-architecture, design, integration and other tasks as part of the chip development and testing processes.
Requirements (experience and expertise areas)
Must have:
• 5+ years of experience in VLSI design.
• Deep knowledge in Verilog.
• Experience in micro-architecture and design of complex blocks.
• Familiar with the verification process of a block (test plan, coverage, etc.).
• Excellent communication skills in English (written and verbal).
Not a must, but an advantage:
• Knowledge in networking and networking chips.
• Experience with multi-clock domain designs.
• Script knowledge (TCL, perl, etc.).
• Understanding the timing closure process (synthesis/STA).
• Understanding DFT.
• Understanding the entire chip development flow.
Requirements (behavioral attributes)
• Strong execution orientation.
• Thorough and accurate.
• Good communicator.
• Open minded.
Requirements (Educational)
• BSc. / MSc. university degree in EE/CS, graduation with honors.
======================================================================================
ASIC Verification Engineer
Job Grade E4, Engineer Staff
Hiring Location(s) Ramat Gan, Israel
Regular Full-time
Planned start date, and if appropriate, planned term date (term date for Interns, Temps, or Contractors) 11/1/2016
Budgeted salary range (local currency): Salary average for his grade for this level: 391000 NIS. Salary will be match according to the candidate experience.
Role & responsibilities
• Key Responsibilities
• Additional individual Contributor / Technical responsibilities AND/OR People Management responsibilities
Join a verification team responsible for the verification of state of the art networking ASIC designs.
As part of the verification effort, new and advanced re-use methodologies are used. Full verification flow block-level to sub-chip and full-chip benches, formal verification and many more.
Requirements (experience and expertise areas)
• Must have experience in ASIC Verification using one of the following HVLs: Specman , SystemVerilog
• Must have experience with advanced verification methodologies (constraint random, coverage driven, verification reuse) as UVM , eRM, VMM, OVM
• Knowledge in Ethernet - an advantage
• Knowledge in PCIe - an advantage
• Experience with Formal Verification - an advantage
• Good knowledge in Verilog HDL - an advantage
• Experience with scripting - an advantage
Requirements (behavioral attributes)
• Initiative
• Ownership
• Open minded
• Strong execution orientation
Requirements (Educational)
• Must have an engineering degree in EE/CS from a well-known university (Technion, Tel Aviv, Ben Gurion…) with high GPA
=============================================================================================
ASIC Formal Verification Engineer
Job Grade E5, Engineer Principal
Hiring Location(s) Ramat Gan, Israel
Regular Full-time
Planned start date, and if appropriate, planned term date (term date for Interns, Temps, or Contractors) 11/1/2016
Budgeted salary range (local currency): Salary average for his grade for this level: 454000 NIS. Salary will be match according to the candidate experience.
Role & responsibilities
• Key Responsibilities
• Additional individual Contributor / Technical responsibilities AND/OR People Management responsibilities
Join a verification team responsible for the verification of state of the art networking ASIC designs.
As part of the verification effort, new and advanced re-use methodologies are used. Full verification flow block-level to sub-chip and full-chip benches, formal verification and many more.
In this role, you’ll lead & develop hands-on the formal verification activity for the project.
Requirements (experience and expertise areas)
• Must have experience in Formal Verification methodologies
• Must have excellent knowledge in Verilog
• Must have good scripting skills (Tcl, Python, Perl)
• Experience with advanced verification methodologies (constraint random, coverage driven, verification reuse) as UVM , eRM, VMM, OVM - an advantage
Requirements (behavioral attributes)
• Initiative
• Ownership
• Open minded
• Strong execution orientation
Requirements (Educational)
• Must have an engineering degree in EE/CS from a well-known university (Technion, Tel Aviv, Ben Gurion…) with high GPA
================================================================================================
ASIC Verification Engineer
Job Grade E3, Engineer Senior (QLogic’s title)
Hiring Location(s) Ramat Gan, Israel
Regular Full-time
Planned start date, and if appropriate, planned term date (term date for Interns, Temps, or Contractors) 11/1/2016
Budgeted salary range (local currency): Salary average for his grade for this level: 312000 NIS. Salary will be match according to the candidate experience.
Role & responsibilities
• Key Responsibilities
• Additional individual Contributor / Technical responsibilities AND/OR People Management responsibilities
Join a verification team responsible for the verification of state of the art networking ASIC designs.
As part of the verification effort, new and advanced re-use methodologies are used. Full verification flow block-level to sub-chip and full-chip benches, formal verification and many more.
Requirements (experience and expertise areas)
• Must have experience in ASIC Verification using one of the following HVLs: Specman , SystemVerilog
• Must have experience with advanced verification methodologies (constraint random, coverage driven, verification reuse) as UVM , eRM, VMM, OVM
• Knowledge in Ethernet - an advantage
• Knowledge in PCIe - an advantage
• Experience with Formal Verification - an advantage
• Good knowledge in Verilog HDL - an advantage
• Experience with scripting - an advantage
Requirements (behavioral attributes)
• Initiative
• Ownership
• Open minded
• Strong execution orientation
Requirements (Educational)
• Must have an engineering degree in EE/CS from a well-known university (Technion, Tel Aviv, Ben Gurion…) with high GPA
Job Grade Principal
Hiring Location(s) Ramat Gan, Israel
Regular Full-time
Requisition type: Replacement / Addition / Immigration / Extension / Conversion Addition
Planned start date, and if appropriate, planned term date (term date for Interns, Temps, or Contractors) 10/1/2016
Budgeted salary range (local currency): Salary average for his grade for this level: XXX NIS. Salary will be match according to the candidate’s experience.
Role & responsibilities
• Key Responsibilities
• Additional individual Contributor / Technical responsibilities AND/OR People Management responsibilities
Member of the design team that is responsible for developing complex, state of the art high-speed Ethernet controller chips.
The candidate will own tasks such as micro-architecture, design, integration and other tasks as part of the chip development and testing processes.
Requirements (experience and expertise areas)
Must have:
• 5+ years of experience in VLSI design.
• Deep knowledge in Verilog.
• Experience in micro-architecture and design of complex blocks.
• Familiar with the verification process of a block (test plan, coverage, etc.).
• Excellent communication skills in English (written and verbal).
Not a must, but an advantage:
• Knowledge in networking and networking chips.
• Experience with multi-clock domain designs.
• Script knowledge (TCL, perl, etc.).
• Understanding the timing closure process (synthesis/STA).
• Understanding DFT.
• Understanding the entire chip development flow.
Requirements (behavioral attributes)
• Strong execution orientation.
• Thorough and accurate.
• Good communicator.
• Open minded.
Requirements (Educational)
• BSc. / MSc. university degree in EE/CS, graduation with honors.
======================================================================================
ASIC Verification Engineer
Job Grade E4, Engineer Staff
Hiring Location(s) Ramat Gan, Israel
Regular Full-time
Planned start date, and if appropriate, planned term date (term date for Interns, Temps, or Contractors) 11/1/2016
Budgeted salary range (local currency): Salary average for his grade for this level: 391000 NIS. Salary will be match according to the candidate experience.
Role & responsibilities
• Key Responsibilities
• Additional individual Contributor / Technical responsibilities AND/OR People Management responsibilities
Join a verification team responsible for the verification of state of the art networking ASIC designs.
As part of the verification effort, new and advanced re-use methodologies are used. Full verification flow block-level to sub-chip and full-chip benches, formal verification and many more.
Requirements (experience and expertise areas)
• Must have experience in ASIC Verification using one of the following HVLs: Specman , SystemVerilog
• Must have experience with advanced verification methodologies (constraint random, coverage driven, verification reuse) as UVM , eRM, VMM, OVM
• Knowledge in Ethernet - an advantage
• Knowledge in PCIe - an advantage
• Experience with Formal Verification - an advantage
• Good knowledge in Verilog HDL - an advantage
• Experience with scripting - an advantage
Requirements (behavioral attributes)
• Initiative
• Ownership
• Open minded
• Strong execution orientation
Requirements (Educational)
• Must have an engineering degree in EE/CS from a well-known university (Technion, Tel Aviv, Ben Gurion…) with high GPA
=============================================================================================
ASIC Formal Verification Engineer
Job Grade E5, Engineer Principal
Hiring Location(s) Ramat Gan, Israel
Regular Full-time
Planned start date, and if appropriate, planned term date (term date for Interns, Temps, or Contractors) 11/1/2016
Budgeted salary range (local currency): Salary average for his grade for this level: 454000 NIS. Salary will be match according to the candidate experience.
Role & responsibilities
• Key Responsibilities
• Additional individual Contributor / Technical responsibilities AND/OR People Management responsibilities
Join a verification team responsible for the verification of state of the art networking ASIC designs.
As part of the verification effort, new and advanced re-use methodologies are used. Full verification flow block-level to sub-chip and full-chip benches, formal verification and many more.
In this role, you’ll lead & develop hands-on the formal verification activity for the project.
Requirements (experience and expertise areas)
• Must have experience in Formal Verification methodologies
• Must have excellent knowledge in Verilog
• Must have good scripting skills (Tcl, Python, Perl)
• Experience with advanced verification methodologies (constraint random, coverage driven, verification reuse) as UVM , eRM, VMM, OVM - an advantage
Requirements (behavioral attributes)
• Initiative
• Ownership
• Open minded
• Strong execution orientation
Requirements (Educational)
• Must have an engineering degree in EE/CS from a well-known university (Technion, Tel Aviv, Ben Gurion…) with high GPA
================================================================================================
ASIC Verification Engineer
Job Grade E3, Engineer Senior (QLogic’s title)
Hiring Location(s) Ramat Gan, Israel
Regular Full-time
Planned start date, and if appropriate, planned term date (term date for Interns, Temps, or Contractors) 11/1/2016
Budgeted salary range (local currency): Salary average for his grade for this level: 312000 NIS. Salary will be match according to the candidate experience.
Role & responsibilities
• Key Responsibilities
• Additional individual Contributor / Technical responsibilities AND/OR People Management responsibilities
Join a verification team responsible for the verification of state of the art networking ASIC designs.
As part of the verification effort, new and advanced re-use methodologies are used. Full verification flow block-level to sub-chip and full-chip benches, formal verification and many more.
Requirements (experience and expertise areas)
• Must have experience in ASIC Verification using one of the following HVLs: Specman , SystemVerilog
• Must have experience with advanced verification methodologies (constraint random, coverage driven, verification reuse) as UVM , eRM, VMM, OVM
• Knowledge in Ethernet - an advantage
• Knowledge in PCIe - an advantage
• Experience with Formal Verification - an advantage
• Good knowledge in Verilog HDL - an advantage
• Experience with scripting - an advantage
Requirements (behavioral attributes)
• Initiative
• Ownership
• Open minded
• Strong execution orientation
Requirements (Educational)
• Must have an engineering degree in EE/CS from a well-known university (Technion, Tel Aviv, Ben Gurion…) with high GPA