Informing myself!
I'm gonna summarize my understanding of the PS2's hardware at this point to see where I need to go from here and maybe speculate on how I'm going to tackle this BEAST.
GENERAL OVERVIEW
From the super super high level block diagram, it's not such a complicated story. The core consists of four main elements: The I/O processor, the Emotion Engine, the sound processor and the Graphics Synthesizer.
The I/O processor is what you'd imagine-- it handles input from controllers, the USB ports, firewire, etc. Like any I/O controller, it interprets signals from I/O peripherals and forwards the logic to, well, in this case, the Emotion Engine (EE from now on).
The sound processor and Graphics Synth generate sound and video output respectively. Dur.
What's special about this whole mess is the EE. The EE is the heart of the PS2; the reason everyone was flipping shits about terrorists buying a gaming console to make missile-launching computers or whatever. Ultimately, the EE is responsible for feeding the sound processor and Graphics Synth with the information that allows them to perform their respective tasks.
Emotion Engine
The general purpose of the Emotion Engine is, again, to feed the sound and graphics processors. For the graphics processor, this means display lists (series of transformations and rendering commands that will hopefully contribute to the construction of a scene).
Now for the most pertient aspect of the EE, the architecture!
The EE's CPU is a MIPS III-based custom chip with some MIPS IV instructions tacked onto it. The core has two coprocessor slaves: a FP coprocessor to handle general FP calculations, and a 128-bit vector processing unit (VU0) for vector calculations. Additionally, we have an IPU (Image Processing Unit-- essentially an MPEG2 decoding unit with some extra features), a 10-channel DMA controller and a Graphics Interface Unit (GIF). There's some other hardware on there as well, but nothing of particular interest at the moment (RDRAM interface and I/O interface).
The CPU/VU0/FPU "team," if you will, is usually responsible for more general-purpose calculations. There are dedicated 128-bit busses between the CPU and both of its coprocessors, as well as 16k of SPRAM (scratch-pad RAM) shared between the CPU and the VPU to get quick 'n dirty work done on small data structures.
The other big "team" in the EE consists of VU1 and the Graphics Synthesizer, which communicate through the GIF over a 128-bit dedicated bus. Unlike in the above team, there's no master/slave relationship here.
The design lends itself to assigning different components specific roles, but everything can be used in a general-purpose fashion, or either "team" can be used to generate display lists in parallel, whatever. It's up to the application writer/compiler writer to designate roles to the different components.
The CPU
The CPU is a standard MIPS III-based chip with 32 128-bit GPRs plus some multimedia instruction set enhancements.
Other factoids:
-16k I-cache (2-way associative)
-8K D-cache (2-way associative)
-6-stage pipeline
-2 64-bit ALU units
-Some other extra SIMD instructions to take advantage of VU0
-The aforementioned SPRAM has its own address space through the store/load instructions
VPU0 and VPU1
Both vector processor units are microarchitecturally identical, but their roles are very different. They are both 128-bit SIMD/VLIW chips, although VPU0 typically serves as a coprocessor for the CPU rather than executing its own VLIW programs. The VPUs have 32 128-bit FP registers, each of which can hold 4 32-bit single precision FP numbers. There are also 16 16-bit integer registers for simple integer operations.
Each vector processor has two execution units, the first of which is composed of 4 FMACs (floating-point multiply-accumulators) and 1 FDIV (floating point division unit). The second contains 1 LSU (dunno), 1 ALU and random number generator. With VLIW instructions both execution units can be used simultaneously-- although again, this typically doesn't apply to VU0 (though it can be put into SIMD/VLIW mode).
VU1 is different from VU0 in that it has an extra FMAC and FDIV (coupled, they are coined the Elementary Functional Unit), and also has 16k of both data and instruction memory as opposed to the 8k/8k available to VU0. VU1 also has multiple paths to get to the GIF: Direct access via a dedicated 128-bit bus (just like VU0) or DMA.
Also, VU1 is completely independent and functions by receiving data/instruction data in the form of display lists. Hence, it works on the SIMD/VLIW instructions to do its stuff and provide the graphics synthesizer with the proper output.
Phew. That was all basically a summary of the article I linked in the previous entry for my own benefit, so I can get a better grasp on the concepts. There are nice block diagrams and more detailed explanations in the article-- I'd suggest checking those out for those interested in knowing... more than what I've spewed here.
THE END.
GENERAL OVERVIEW
From the super super high level block diagram, it's not such a complicated story. The core consists of four main elements: The I/O processor, the Emotion Engine, the sound processor and the Graphics Synthesizer.
The I/O processor is what you'd imagine-- it handles input from controllers, the USB ports, firewire, etc. Like any I/O controller, it interprets signals from I/O peripherals and forwards the logic to, well, in this case, the Emotion Engine (EE from now on).
The sound processor and Graphics Synth generate sound and video output respectively. Dur.
What's special about this whole mess is the EE. The EE is the heart of the PS2; the reason everyone was flipping shits about terrorists buying a gaming console to make missile-launching computers or whatever. Ultimately, the EE is responsible for feeding the sound processor and Graphics Synth with the information that allows them to perform their respective tasks.
Emotion Engine
The general purpose of the Emotion Engine is, again, to feed the sound and graphics processors. For the graphics processor, this means display lists (series of transformations and rendering commands that will hopefully contribute to the construction of a scene).
Now for the most pertient aspect of the EE, the architecture!
The EE's CPU is a MIPS III-based custom chip with some MIPS IV instructions tacked onto it. The core has two coprocessor slaves: a FP coprocessor to handle general FP calculations, and a 128-bit vector processing unit (VU0) for vector calculations. Additionally, we have an IPU (Image Processing Unit-- essentially an MPEG2 decoding unit with some extra features), a 10-channel DMA controller and a Graphics Interface Unit (GIF). There's some other hardware on there as well, but nothing of particular interest at the moment (RDRAM interface and I/O interface).
The CPU/VU0/FPU "team," if you will, is usually responsible for more general-purpose calculations. There are dedicated 128-bit busses between the CPU and both of its coprocessors, as well as 16k of SPRAM (scratch-pad RAM) shared between the CPU and the VPU to get quick 'n dirty work done on small data structures.
The other big "team" in the EE consists of VU1 and the Graphics Synthesizer, which communicate through the GIF over a 128-bit dedicated bus. Unlike in the above team, there's no master/slave relationship here.
The design lends itself to assigning different components specific roles, but everything can be used in a general-purpose fashion, or either "team" can be used to generate display lists in parallel, whatever. It's up to the application writer/compiler writer to designate roles to the different components.
The CPU
The CPU is a standard MIPS III-based chip with 32 128-bit GPRs plus some multimedia instruction set enhancements.
Other factoids:
-16k I-cache (2-way associative)
-8K D-cache (2-way associative)
-6-stage pipeline
-2 64-bit ALU units
-Some other extra SIMD instructions to take advantage of VU0
-The aforementioned SPRAM has its own address space through the store/load instructions
VPU0 and VPU1
Both vector processor units are microarchitecturally identical, but their roles are very different. They are both 128-bit SIMD/VLIW chips, although VPU0 typically serves as a coprocessor for the CPU rather than executing its own VLIW programs. The VPUs have 32 128-bit FP registers, each of which can hold 4 32-bit single precision FP numbers. There are also 16 16-bit integer registers for simple integer operations.
Each vector processor has two execution units, the first of which is composed of 4 FMACs (floating-point multiply-accumulators) and 1 FDIV (floating point division unit). The second contains 1 LSU (dunno), 1 ALU and random number generator. With VLIW instructions both execution units can be used simultaneously-- although again, this typically doesn't apply to VU0 (though it can be put into SIMD/VLIW mode).
VU1 is different from VU0 in that it has an extra FMAC and FDIV (coupled, they are coined the Elementary Functional Unit), and also has 16k of both data and instruction memory as opposed to the 8k/8k available to VU0. VU1 also has multiple paths to get to the GIF: Direct access via a dedicated 128-bit bus (just like VU0) or DMA.
Also, VU1 is completely independent and functions by receiving data/instruction data in the form of display lists. Hence, it works on the SIMD/VLIW instructions to do its stuff and provide the graphics synthesizer with the proper output.
Phew. That was all basically a summary of the article I linked in the previous entry for my own benefit, so I can get a better grasp on the concepts. There are nice block diagrams and more detailed explanations in the article-- I'd suggest checking those out for those interested in knowing... more than what I've spewed here.
THE END.